An SOI substrate conventionally comprises a semiconductor film (or top semiconductor layer) located on top of a buried insulating layer (generally of silicon oxide), which is commonly designated by the acronym BOX (for Buried OXide), itself located on top of a carrier substrate, a bulk substrate for example.
High-performance radio-frequency (RF) integrated circuits are generally fabricated on what are referred to as high-resistivity (HR) p-doped semiconductor substrates, i.e. substrates with a resistivity typically higher than 1 kohm·cm, so as to limit losses in the substrate and crosstalk between neighboring components due to conduction.
Furthermore, it is common to use silicon-on-insulator (SOI) HR substrates. The passive or active components formed in and on the top semiconductor layer are then insulated from the bulk substrate by the buried oxide layer.
However, it has been observed that although using such substrates decreases losses related to the substrate, it does not completely prevent them. Specifically, stationary positive electric charges are inevitably present in the BOX due to the fabrication process of this oxide layer. Said charges are responsible for the accumulation in the substrate, in the vicinity of the BOX, of mobile electric charges (electrons) that are able to form a conductive channel. Thus, even if HR substrates are used, parasitic surface conduction in the substrate leads to Joule losses as a result of eddy currents.
Furthermore, the insulated silicon/BOX/substrate stack behaves as a metal oxide semiconductor (MOS) capacitor. To a first approximation, the thickness of the inversion layer associated with this MOS capacitor is considered to vary inversely with the square root of the dopant concentration of the substrate. Therefore, it will be understood that this thickness is correspondingly larger when the substrate is an HR substrate, i.e. weakly doped. The capacitance of this capacitor has the property of being modulated by the electric potential applied to the components formed in or on the insulated silicon film, opposite and above the BOX. This modulated parasitic capacitance is responsible for harmonic distortions and crosstalk affecting the RF components of integrated circuits in a way that is detrimental to the performance of these components. Such distortion may in particular be quantified by the third-order intercept point (abbreviated TOIP or IP3) method.
In order to mitigate this effect, it is known to use more complex carrier substrate structures, incorporating a specific region separating the single-crystal portion of the carrier substrate and the BOX so as to create, near the BOX, a high density of surface states capable of trapping free carriers. This trapping of free carriers by surface states greatly decreases the effect of parasitic surface conduction. Furthermore it leads to pinning of the Fermi level in the semiconductors at the substrate/BOX interface, thereby making the capacitance of the parasitic MOS capacitor largely independent of the electric potential applied to the components formed opposite, above the BOX, and thus limiting harmonic distortions. Such substrates are qualified “trap-rich”.
The document “SOT technology: An Opportunity for RF Designers,” Journal of Telecommunications and Information Technology, 04/2009 (incorporated by reference) describes a particularly effective method for forming a trap-rich layer under the BOX of an SOI substrate, consisting in forming a carrier substrate comprising a polysilicon layer inserted between the single-crystal portion of the carrier substrate and the BOX. Specifically, discontinuities in the crystal structure at the grain boundaries of the polysilicon act as charge traps. Such a layer may be formed by depositing on the single-crystal substrate, before the BOX has been formed, a polysilicon or amorphous silicon layer, by way of low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), this deposition operation being followed by a stabilization and/or recrystallization anneal. To ensure that a polycrystalline layer is indeed obtained rather than simple epitaxy from the single-crystal substrate, it is necessary to form on the latter, before the silicon is deposited, an interface layer that blocks epitaxial growth. A silicon oxide layer of less than 1 nm in thickness, obtained by chemical or thermal oxidation, is sufficient for this purpose.
In order to increase the density of traps, it is desirable to increase the density of grain boundaries at the polysilicon/BOX interface, i.e. to decrease the average width of the grains at this interface. Unfortunately, the inventors have observed that the growth of the polysilicon obtained by CVD is of the ‘divergent’ pseudo-columnar type, i.e. the grains have substantially the shape of inverted cones that widen between the bottom of the layer and its top. The average width of the grains is therefore maximal at the top of the polysilicon layer, i.e. at the polysilicon/BOX interface, and therefore the density of traps per unit area at this interface is not optimal.
However, in order to ensure the single-crystal portion of the carrier substrate is separated from the BOX and the components produced on the thin layer located on top of the BOX by a large enough distance, the polysilicon layer must be at least 1000 nm to 5000 nm in thickness, and, as a result, the average width of the polysilicon grains at the polysilicon/BOX interface is then about 200 nm to 1000 nm. For RF components in 90 nm or 65 nm technology or lower, this therefore means that the average width of the polysilicon grains at the interface with the BOX is larger than the lateral dimension of the elementary transistors above the BOX. Thus, depending on the location of the components above the BOX, transistors for example, said components will randomly either be plumb with a single grain or a plurality of grains. This leads to a dispersion in the electrical parameters of the transistors since the density of traps under a transistor depends on its position with respect to the grains.
The inventors have observed that forming the polysilicon layer by controlled recrystallization of an amorphous silicon layer does not substantially decrease the average size of the grains of polysilicon at the polysilicon/BOX interface. Specifically, a minimum thermal budget is required to sufficiently stabilize a multilayer substrate and to make it thermomechanically stable enough to be able to used as a starting substrate for the fabrication of integrated circuits. This thermal budget leads to a polysilicon layer the grain size of which is equal to or larger than that obtained by depositing a polysilicon layer directly on the bulk substrate.
There is therefore a need for a method for fabricating an SOI substrate that remedies all or some of the above drawbacks.